1. Field of the Invention
This invention relates to a dynamic random access memory (hereinafter referred to as a DRAM) system, and more particularly to an on-chip DRAM system incorporating a pre-decoder means.
2. Description of the Prior Art
Conventional DRAM systems have a memory refreshing function in which memory cells are refreshed in response to address signals (Data) which are internally generated on the DRAM chip. The internal address signal is generated when an inverted row address strobe (RAS) signal changes from a high level to a low level after an inverted column address strobe (CAS) signal goes, for example, from a high level to a low level. The DRAM system also includes a row pre-decoder which switches an external address signal and an internal address signal to the row address decoder.
A prior art DRAM system, for example, includes a row address buffer 5 as shown in FIG. 5. The row address buffer 5 includes a switching means 11 which receives external address signals AD0 to ADN when an address switching signal CBR, which is output from a CBR control signal is at a low level, and receives internal address signals A0 to AN when the CBR signal is at a high level. A buffer circuit 12 is connected to the output of the switching means 11, and is activated by an address buffer enabling signal ABE of a high level to output row address signals RA0 to RAN to a row pre-decoder 7.
In the CBR refreshing operation, the buffer circuit 12 is activated by a high level signal ABE after switching of the switching means 11 has been completed, since the buffer circuit 12 may be erroneously operated when either the external address state or internal address state is undecided. Hence, the CBR control circuit is designed so as to operate at such a speed that its switching signal CBR is output before the buffer circuit 12 is activated, as shown in FIG. 7.
However, the prior art DRAM system has the following disadvantages. In FIG. 7, when the address switching signal CBR is at the TTL level, and both the column and row address strobe signal CAS and RAS respectively are in a stand-by state, a current I (for example, 300 uA) flows through NMOS transistors in a NAND gate, thus consuming electic power. Also, the conventional CBR control circuit requires large MOS transistors for an AND gate to output a high level signal CBR faster than the ABE signal as shown in FIG. 7. This results in an increase in power consumption in the stand-by condition. Shortening the interval between the CBR and ABE signals to decrease power consumption in the stand-by condition may cause erroneous operation. For these reasons, it has been difficult to obtain an improved DRAM system which can achieve less power consumption in the stand-by state.